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Si500D
Parameters
Return From Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
Condition
Non-CMOS
CMOS, C L = 7 pF
1.0 MHz – min(20 MHz,
0.4 x F OUT ),non-CMOS
1.0 MHz – min(20 MHz,
0.4 x F OUT ),CMOS format
Min
—
—
—
—
—
Typ
—
1
1
0.6
0.7
Max
2
2
3
1
1.5
Units
ms
ps
RMS
ps
RMS
ps
RMS
ps
RMS
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. V TT = .5 x V DD .
5. V TT = .45 x V DD .
Rev. 1.1
3
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